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@carrioresearch · 2026-10-14 12:02

$MU $SKHY $CXMT Fair point🫡. Cycle time per wafer does go up when a layer has to be exposed two or three times. Here's how it works out for $CXMT, which makes DRAM on DUV only, with no EUV: 1. Only the critical layers get split. A DRAM flow runs dozens of mask layers, and only the finest few (word lines, bit lines, the capacitor array) need 2-3 exposures. Everything else is a single pass. Total steps go up, but the whole line doesn't run 2-3x slower. 2. A slower wafer doesn't mean lower output. Each wafer spends longer in the fab, but monthly output is set by how many tools run in parallel. 3. The bill lands on capex and yield. Every extra exposure adds another round of overlay error and defect risk, plus extra etch and deposition steps. That's where CXMT's cost gap comes from. DK Semi lab's summary puts it at more than 30%. At today's DRAM contract prices, CXMT can carry that gap and still make good money. Makers running EUV on those layers skip most of that cost, so as long as AI servers keep setting DRAM prices, $MU and $SKHY have the most room on margins.

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