Google's next TPU moves to Intel packaging has people thinking TSMC just lost … · @Leoskie_L · TwKit

@Leoskie_L

Google's next TPU moves to Intel packaging has people thinking TSMC just lost CoWoS business. The first thing that gets stuck isn't Intel's technology. It's a substrate. Coming back from an Asia trip, KeyBanc says yields on the substrate for Intel's EMIB-T packaging are roughly 50–60% at Ibiden and only 20–30% at Unimicron. These are analyst estimates, not company disclosures. But if they're right, that's a big gap. Do the math: to get 100 good substrates, Ibiden has to start 167–200, and Unimicron has to start 333–500. EMIB-T doesn't use one big silicon interposer. You cut cavities into the substrate, embed small silicon bridges, then laminate ABF build-up layers on top. A cavity slightly off, or a bridge not sitting flat, and the whole panel is scrap. It's like frying eggs in a huge pan. The pan size is easy. The hard part is landing every yolk dead center in a tiny dimple, and one off-center yolk means you redo the whole batch. KeyBanc itself says these yields could cap Google's Humufish (TPU v9) at around 5–6 million units. In other words, Intel won a ticket, not capacity. Turning the ticket into shipments depends on how fast Ibiden and Unimicron can pull yields up. On TSMC's side, C.C. Wei was asked on the earnings call whether TSMC would step in as backup if a rival can't deliver. He first said he'd rather not go there, then added that the hint was clear enough. Last cycle everyone worried about not enough CoWoS. This cycle it's someone else's substrate. The bottleneck didn't go away. It moved. I went in thinking this was an Intel comeback story. Turns out the main character might be a substrate that's still learning to fry an egg. $INTC $TSM $GOOGL Ibiden 4062.T Unimicron http://3037.TW #EMIB #CoWoS 下午3:33CoS Headline: "Japan approves TSMC 3nm in Kumamoto." First reaction from most people: Japan is throwing money around again. Look closer and the subsidy cap actually went down. On Oct 16, Japan's trade ministry (METI) approved a revised plan for Kumamoto Fab 2: from 6–12nm to all 3nm. That makes it Japan's first 3nm production. Now the numbers. The old plan was 48,000 wafers a month. Phase one of the new plan is 6,000. That's one-eighth. The subsidy cap went down with it, from ¥732.0B to ¥645.15B, about 12% less. Here's the odd part: fewer wafers, but no less money. The investment actually rises to more than $15.7B, and METI says it will look at raising the subsidy. The reason is that 3nm needs EUV tools, and each one costs a fortune. Fewer wafers means each one carries a much bigger share of the equipment bill. It's like turning a planned big-box store into a jewelry boutique. Same floor space, fewer shelves, but every display case needs a safe. TSMC's own wording is cautious: production will be "phased" according to market demand, and it's conditional on continued Japanese government support. Shipments start December 2028. So this isn't TSMC racing into Japan. It's more like Japan wants 3nm, TSMC says fine, but let's settle the bill first. Fab 1 changed too. It was planned at 55,000 wafers a month across 22–28nm and 12–16nm. Now 12–16nm is dropped, leaving 22–28nm only, at 45,000 a month. Drop the middle nodes on one side, jump straight to 3nm on the other. Japan is skipping several generations. I thought this was a story about Japan doubling down. After the numbers, it reads more like Japan paid a deposit and the rest comes later. http://www.jiji.com/article http://www.chinatimes.com/newspapers $TSM http://2330.TW #TSMC #Kumamoto #3nm #semiconductors

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