$MU $TSM $SNDK $FORM $TER Micron's roadmap to 2030 needs more wafer for every … · @carrioresearch · TwKit

@carrioresearch

$MU $TSM $SNDK $FORM $TER Micron's roadmap to 2030 needs more wafer for every bit at each step, so the memory shortage is written into the plan, and the extra steps get paid out to foundries and testers. Micron's October 21 tech webinar: 1. Scott DeBoer, Micron's president and technology chief, repeated Sanjay's line that memory stays short for the next two years, then went a step further: "we actually don't see a time when it comes into balance." The why came from his own product list. HBM4E is targeted for 2027, and vertical HBM, which is DRAM stacked straight on top of the GPU, arrives next to HBM5 in 2028. He said vertical HBM carries "a very high trade ratio," meaning fewer DRAM dies out of each wafer, and that the ratio keeps climbing all the way to the edge version, vEIM: "that pressure remains through this roadmap." So the same bits need more wafers at every step, and supply has to keep running just to stand still. 2. The base die is moving to a foundry. Micron built HBM4's in-house while "some competitors" went outside, and from HBM4E both standard and custom parts go to a foundry node. He didn't name the foundry, though $TSM already makes the base die for SK hynix's HBM4 according to April press reports, so that's where I'd look first. 3. $MU's own next steps, the 1-delta DRAM node and G11 NAND at more than 400 layers, both ramp in the second half of 2027. 4. He was blunt on NAND. Micron won't put high-bandwidth flash along the GPU's shoreline because "we don't think that has merit," and that's pretty much where $SNDK's HBF is designed to sit. It's a rival talking, so some salt is fair, but on this roadmap HBF doesn't get Micron as a second source. 5. My read on test: more wafers per bit and taller stacks per package mean more wafers to probe and more die to sort, which is volume for $FORM and $TER. 6. The soft spot came from Bank of America, which asked whether inference chips might carry less DRAM than training chips. DeBoer said more memory always makes a better system and left it there, with no number. Every date above is also the seller's own target, and those usually run early. 7. I'd still lean on the wafer math more than the balance quote. It sits in Micron's own 2028 to 2030 product list, and each step on that list eats more silicon per bit than HBM4 does today.

曝光 343 · 评论 0 · 点赞 5 · 书签 2