$INTC: Future AI packages could use at least 70 EMIB bridges Intel expects EMI… · @LIWEI_TWCapital · TwKit

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$INTC: Future AI packages could use at least 70 EMIB bridges Intel expects EMIB bridge counts to rise as AI packages integrate more compute chiplets and HBM stacks, according to ZDNet Korea. The packaging roadmap Commercialized in 2026: Packages up to 120 × 120 mm, with 12 HBM stacks and at least 20 EMIB bridges. Under development: Packages of at least 120 × 180 mm, with 16 or more HBM stacks and at least 38 bridges. Future configuration: A 240 × 240 mm package with at least 32 HBM stacks and 70 bridges. No commercialization date was given. Why EMIB scales differently EMIB embeds small silicon bridges in the package substrate to connect adjacent compute chiplets and HBM. This avoids the need for a large silicon interposer across the entire package. Intel says the smaller bridges can be packed more densely onto a wafer, achieving over 90% wafer utilization versus roughly 60% for large interposers. That figure measures wafer area usage, not the yield of finished packages. What EMIB-T adds EMIB-T introduces through-silicon vias and capacitors to improve power delivery and manage noise, supporting HBM4 and high-speed connections. As AI packages grow, each package could require substantially more bridges. The 70-bridge configuration is a future design, not a confirmed customer order. Intel Technical Brief: https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-11/intel-foundry-hpc-ai-brief.pdf

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